SME
Digital Logic Design · Problem type
Ripple-carry adder delay
Use this for “A 32-bit ripple-carry adder has 0.5 ns of carry delay per bit. How long does an add take, and how fast can it run?”
Diagram
The carry ripples through 32 full adders, tc = 0.5 ns each: t = 32 × 0.5 ns = 16 ns.
One
add
fits
in
one
clock
period,
so
fₘₐₓ
=
1
t
:
fₘₐₓ
=
62.5
MHz.
Each sum bit is right only once the carry into it has settled; the top one waits for all n.
This is an example. Type your own values to start a new problem.
t (ns)
=
n
×
tc (ns)
fₘₐₓ (MHz)
=
1
÷
t (ns)
Formulas
t
=
n
×
tc
16 = 32 × 0.5
fₘₐₓ
=
1,000
t
62.5
=
1,000
16
Assumptions
•
Each full adder passes its carry on after the same delay tc.
•
The worst case is a carry made in the lowest bit that ripples through all n bits to the top.
•
The fastest clock gives the adder one whole period; register delays are left out.
Step-by-step
WE KNOW
n = 32, tc = 0.5 ns
FIND
adder delay (t), fastest clock (fₘₐₓ)
Step 1 · Find adder delay (t)
Use t = n × tc
Each
bit
waits
for
the
carry
from
the
bit
below,
so
the
n
carry
delays
add
up.
t
=
32
×
0.5
t
=
16
ns
Step 2 · Find fastest clock (fₘₐₓ)
Use fₘₐₓ = 1,000 ÷ t
One
add
fits
in
one
period;
1000
turns
1
ns
into
MHz.
fₘₐₓ
=
1,000
16
fₘₐₓ = 62.5 MHz
Check
Put the numbers back in. Both sides should match.
16 = 32 × 0.5 ✓
62.5
=
1,000
16
✓
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